Complimentary metal oxide semiconductor (CMOS) structures are the core active elements of modern electronics. Undoubtedly, the major material enabling features of Si CMOS are the superb quality of the native silicon dioxide (SiO2), Si/SiO2 interface and high crystalline perfection of the Si substrates. The field effect transistor (FET) implemented as CMOS is scalable. That is, speed and complexity improves with decreasing device feature sizes. This concept makes CMOS architecture a powerful methodology. Deep submicron room-temperature bulk Si CMOS is presently the main technology used for ultra large scale integrated circuits (ULSICs).
Continued scaling of current CMOS architecture is reaching the limits of the material properties of both the SiO2 gate dielectric and bulk Si substrate. Silicon-on-insulator (SOI) substrates offer solutions to both ULSI scaling and high performance wireless architectures. High frequency ULSI requires SOI for reduction in the number of processing steps, reduction of substrate leakage current coupling between FET's reducing parasitic capacitances and latchup, formation of shallow junctions, isolation of clock noise and functional regions on chip, etc. SOI CMOS offers a 20-35% performance gain over conventional bulk Si CMOS.
Various attempts have been made at implementing a viable SOI material, with practically all methods focusing on the formation of a relatively thin active layer of Si separated from a substrate material using an insulator or the insulator itself being the substrate. It will be understood by those skilled in the art that the active layer is formed of single crystal silicon (SC) or other well known semiconductor material. In this disclosure the term “crystalline silicon” is also used to denote a layer of silicon that is substantially single crystal material, i.e. as much of a single crystal as can be formed using present day techniques. Early attempts used laser or e-beam recrystallization of amorphous Si into single crystal Si which was deposited on sapphire, quartz or other glass substrates. The results were far from ideal and typically resulted in a domain/polycrystalline active layer with poor uniformity.
Ion implantation of oxygen or nitrogen (or even both) through the surface of a bulk Si substrate has proven to be an efficient method of realizing buried oxide (BOX) layers beneath an active Si layer. Silicon dioxide possesses a very wide band gap, large conduction/valence band offsets with Si and readily forms a thermal oxide when Si atoms are in an oxygen environment. SiO2 is therefore an obvious choice as an insulator material and thus oxygen ion implantation is preferred. High densities of spatially localized oxygen ions can be produced at well controlled depths beneath the Si surface. However, the energetic implanted ions produce a highly defective topmost Si active layer. An aggressive post implant thermal annealing campaign is required to recrystallize the active layer back into low defect density single crystal Si. The result is a single crystal Si active layer on buried oxide insulator layer. However, by its very nature of fabrication this process is limited in the maximum thickness of oxide which can be created beneath the active layer of Si. Further, as understood by those skilled in the art this process is very work intensive with many steps and is therefore expensive and subject to errors.
Recently, a bond and etch back technology has been demonstrated which combines implantation with wafer bonding. It can also potentially offer thick BOX layers. A silicon wafer surface is oxidized to form SiO2 and then implanted with H+ ions to form a relatively uniform thin layer beneath the surface. The wafer is bonded to a second bulk Si wafer initially via Van der Waal's forces. The combined bonded wafer structure is then cleaned and thermally activated such that the H+ ions react to form water and voids/blisters which subsequently forms an atomic cleave plane defined by the hydrogen implant. This technique allows transfer of a thin layer of single crystal Si and amorphous oxide onto a second wafer resulting in an SOI structure. However, to achieve a thin active layer with a sufficiently smooth surface, extensive use of surface polishing is required at the cleaved surface. Chemical mechanical polishing (CMP) and even argon cluster sputtering are used to define the final roughness which can potentially approach that of bulk Si wafers. Further, extensive annealing is required at ˜1100° C. to strengthen bonding and remove defects. This is a costly, complex process and produces unwanted defects.
Another problem with the crystalline silicon on a silicon dioxide insulating layer is the strain produced by stress introduced at the junction by the lattice mismatch between the silicon and the thermally formed silicon dioxide. The lattice mismatch results in a relatively high compressive stress at the junction between the two materials. In many instances this high stress can result in dislocations, crystalline defects, and even fractures in the active layer. Some components can be formed in the crystalline layer that use this compressive stress to an advantage, however, since the compressive stress will be across the entire wafer it will affect all components formed in/on the crystalline layer, many to a highly undesirable degree. To provide an unstressed or unstrained active layer, the thickness of the silicon dioxide layer must be severely limited to a thickness at which the stress substantially disappears. That is, in each atomic layer of the silicon dioxide a small amount of the stress can be removed by lattice matching until, ultimately, all stress is removed (stress distribution). However, the result is a layer of silicon dioxide that is too thick to be of use in many applications, such as gate oxides in very small field effect transistors and the like.
Also, because the silicon dioxide layer allows some migration of impurities into the active layer from the substrate (handle wafer) both of the substrates must be high quality wafers, which adds substantial expense. Further, the silicon dioxide may contain impurities (e.g. hydrogen molecules introduced during the oxidation process) that can migrate into the active layer.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide new and improved method of fabricating semiconductor components in-situ (i.e. without removing the structure from the epitaxial chamber) and in a continuous integrated sequence.
Another object of the invention is to provide new and improved semiconductor-on-insulator semiconductor components.
Another object of the invention is to provide new and improved semiconductor-on-insulator semiconductor components with insulating layers having improved characteristics.